Computer Organization
Q111.
What is the bit rate of a video terminal unit with 80 characters/line, 8 bits/character and horizontal sweep time of 100 \mu s (including 20 \mu s of retrace time)?Q112.
In 8085 microprocessor, the ISR for handling trap interrupt is at which location?Q113.
Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:Q114.
For the daisy chain scheme of connecting I/O devices, which of the following statements is true?Q116.
A computer handles several interrupt sources of which the following are relevant for this question. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high) Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed) Interrupt from Keyboard (raises Interrupt if a key is pressed or released) Interrupt from Hard Disk (raises Interrupt when a disk read is completed)Which one of these will be handled at the HIGHEST priority?Q117.
The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?Q119.
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The TRAP interrupts mechanism of the 8085 microprocessor:Q120.
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interruptsI_1, I_2 and I_3 require the following execution time after the interrupt is recognized: I. I_1 requires 25 microseconds II. I_2 requires 35 microseconds III. I_3 requires 20 microseconds I_1 has the highest priority and I_3 has the lowest. What is the possible range of time for I_3 to be executed assuming that it may or may not occur simultaneously with other interrupts?